Classic Timing Analyzer report for transkod
Wed Oct 12 10:29:13 2011
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 6.704 ns    ; I0   ; E  ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 6.704 ns        ; I0   ; E  ;
; N/A   ; None              ; 6.688 ns        ; I3   ; E  ;
; N/A   ; None              ; 6.578 ns        ; I1   ; E  ;
; N/A   ; None              ; 6.506 ns        ; I0   ; O3 ;
; N/A   ; None              ; 6.505 ns        ; I0   ; O2 ;
; N/A   ; None              ; 6.489 ns        ; I3   ; O2 ;
; N/A   ; None              ; 6.481 ns        ; I0   ; O1 ;
; N/A   ; None              ; 6.476 ns        ; I0   ; O0 ;
; N/A   ; None              ; 6.462 ns        ; I3   ; O1 ;
; N/A   ; None              ; 6.460 ns        ; I3   ; O0 ;
; N/A   ; None              ; 6.459 ns        ; I2   ; E  ;
; N/A   ; None              ; 6.387 ns        ; I1   ; O2 ;
; N/A   ; None              ; 6.359 ns        ; I1   ; O0 ;
; N/A   ; None              ; 6.358 ns        ; I1   ; O1 ;
; N/A   ; None              ; 6.348 ns        ; I3   ; O3 ;
; N/A   ; None              ; 6.259 ns        ; I2   ; O3 ;
; N/A   ; None              ; 6.257 ns        ; I2   ; O2 ;
; N/A   ; None              ; 6.234 ns        ; I2   ; O1 ;
; N/A   ; None              ; 6.228 ns        ; I2   ; O0 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Wed Oct 12 10:29:11 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off transkod -c transkod --timing_analysis_only
Info: Longest tpd from source pin "I0" to destination pin "E" is 6.704 ns
    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_AE14; Fanout = 5; PIN Node = 'I0'
    Info: 2: + IC(1.636 ns) + CELL(0.436 ns) = 3.071 ns; Loc. = LCCOMB_X64_Y3_N16; Fanout = 1; COMB Node = 'inst34'
    Info: 3: + IC(0.835 ns) + CELL(2.798 ns) = 6.704 ns; Loc. = PIN_AC21; Fanout = 0; PIN Node = 'E'
    Info: Total cell delay = 4.233 ns ( 63.14 % )
    Info: Total interconnect delay = 2.471 ns ( 36.86 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Wed Oct 12 10:29:13 2011
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


