Classic Timing Analyzer report for bcd
Wed Oct 19 10:51:38 2011
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clock'
  6. Clock Hold: 'clock'
  7. tco
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                             ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------+----------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From           ; To             ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------+----------------+------------+----------+--------------+
; Worst-case tco               ; N/A                                      ; None          ; 22.774 ns                        ; 74192:inst2|23 ; O0             ; clock      ; --       ; 0            ;
; Clock Setup: 'clock'         ; N/A                                      ; None          ; 68.21 MHz ( period = 14.660 ns ) ; 74192:inst2|23 ; 74192:inst2|23 ; clock      ; clock    ; 0            ;
; Clock Hold: 'clock'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; 74192:inst2|23 ; 74192:inst2|23 ; clock      ; clock    ; 7            ;
; Total number of failed paths ;                                          ;               ;                                  ;                ;                ;            ;          ; 7            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+----------------+----------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                                 ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From           ; To             ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 68.21 MHz ( period = 14.660 ns )               ; 74192:inst2|23 ; 74192:inst2|23 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 84.25 MHz ( period = 11.870 ns )               ; 74192:inst2|24 ; 74192:inst2|24 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 103.11 MHz ( period = 9.698 ns )               ; 74192:inst2|25 ; 74192:inst2|25 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 112.63 MHz ( period = 8.879 ns )               ; 74192:inst2|26 ; 74192:inst2|26 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 167.84 MHz ( period = 5.958 ns )               ; 74192:inst|23  ; 74192:inst|23  ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 226.40 MHz ( period = 4.417 ns )               ; 74192:inst|24  ; 74192:inst|24  ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; 426.80 MHz ( period = 2.343 ns )               ; 74192:inst|25  ; 74192:inst|25  ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; 74192:inst|26  ; 74192:inst|26  ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clock'                                                                                                                                                                     ;
+------------------------------------------+----------------+----------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack                            ; From           ; To             ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+----------------+----------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; 74192:inst2|23 ; 74192:inst2|23 ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst2|24 ; 74192:inst2|24 ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst2|25 ; 74192:inst2|25 ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst2|26 ; 74192:inst2|26 ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst|23  ; 74192:inst|23  ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst|24  ; 74192:inst|24  ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
; Not operational: Clock Skew > Data Delay ; 74192:inst|25  ; 74192:inst|25  ; clock      ; clock    ; None                       ; None                       ; 0.407 ns                 ;
+------------------------------------------+----------------+----------------+------------+----------+----------------------------+----------------------------+--------------------------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+----------------+----+------------+
; Slack ; Required tco ; Actual tco ; From           ; To ; From Clock ;
+-------+--------------+------------+----------------+----+------------+
; N/A   ; None         ; 22.774 ns  ; 74192:inst2|23 ; O0 ; clock      ;
; N/A   ; None         ; 20.196 ns  ; 74192:inst2|24 ; O1 ; clock      ;
; N/A   ; None         ; 17.854 ns  ; 74192:inst2|25 ; O2 ; clock      ;
; N/A   ; None         ; 16.160 ns  ; 74192:inst2|26 ; O3 ; clock      ;
; N/A   ; None         ; 14.316 ns  ; 74192:inst|23  ; O4 ; clock      ;
; N/A   ; None         ; 12.007 ns  ; 74192:inst|24  ; O5 ; clock      ;
; N/A   ; None         ; 9.791 ns   ; 74192:inst|25  ; O6 ; clock      ;
; N/A   ; None         ; 7.474 ns   ; 74192:inst|26  ; O7 ; clock      ;
+-------+--------------+------------+----------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Wed Oct 19 10:51:36 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bcd -c bcd --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Warning: Found 16 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "74192:inst|73" as buffer
    Info: Detected ripple clock "74192:inst|25" as buffer
    Info: Detected gated clock "74192:inst|51" as buffer
    Info: Detected gated clock "74192:inst2|51" as buffer
    Info: Detected gated clock "74192:inst2|73" as buffer
    Info: Detected gated clock "74192:inst|100" as buffer
    Info: Detected ripple clock "74192:inst|24" as buffer
    Info: Detected ripple clock "74192:inst2|24" as buffer
    Info: Detected ripple clock "74192:inst2|25" as buffer
    Info: Detected ripple clock "74192:inst|23" as buffer
    Info: Detected ripple clock "74192:inst|26" as buffer
    Info: Detected ripple clock "74192:inst2|26" as buffer
    Info: Detected gated clock "74192:inst2|100~0" as buffer
    Info: Detected gated clock "74192:inst|77" as buffer
    Info: Detected gated clock "74192:inst2|100" as buffer
    Info: Detected ripple clock "74192:inst2|23" as buffer
Info: Clock "clock" has Internal fmax of 68.21 MHz between source register "74192:inst2|23" and destination register "74192:inst2|23" (period= 14.66 ns)
    Info: + Longest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X62_Y1_N12; Fanout = 1; COMB Node = '74192:inst2|23~1'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest clock skew is -14.039 ns
        Info: + Shortest clock path from clock "clock" to destination register is 5.054 ns
            Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
            Info: 2: + IC(2.404 ns) + CELL(0.149 ns) = 3.415 ns; Loc. = LCCOMB_X62_Y1_N22; Fanout = 5; COMB Node = '74192:inst|77'
            Info: 3: + IC(0.273 ns) + CELL(0.420 ns) = 4.108 ns; Loc. = LCCOMB_X62_Y1_N24; Fanout = 1; COMB Node = '74192:inst2|100'
            Info: 4: + IC(0.409 ns) + CELL(0.537 ns) = 5.054 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
            Info: Total cell delay = 1.968 ns ( 38.94 % )
            Info: Total interconnect delay = 3.086 ns ( 61.06 % )
        Info: - Longest clock path from clock "clock" to source register is 19.093 ns
            Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
            Info: 2: + IC(2.341 ns) + CELL(0.787 ns) = 3.990 ns; Loc. = LCFF_X63_Y2_N17; Fanout = 6; REG Node = '74192:inst|26'
            Info: 3: + IC(0.728 ns) + CELL(0.419 ns) = 5.137 ns; Loc. = LCCOMB_X62_Y1_N26; Fanout = 1; COMB Node = '74192:inst|73'
            Info: 4: + IC(0.408 ns) + CELL(0.787 ns) = 6.332 ns; Loc. = LCFF_X63_Y1_N15; Fanout = 3; REG Node = '74192:inst|25'
            Info: 5: + IC(0.457 ns) + CELL(0.420 ns) = 7.209 ns; Loc. = LCCOMB_X62_Y1_N14; Fanout = 2; COMB Node = '74192:inst|51'
            Info: 6: + IC(0.381 ns) + CELL(0.787 ns) = 8.377 ns; Loc. = LCFF_X61_Y1_N17; Fanout = 4; REG Node = '74192:inst|24'
            Info: 7: + IC(0.506 ns) + CELL(0.393 ns) = 9.276 ns; Loc. = LCCOMB_X62_Y1_N18; Fanout = 1; COMB Node = '74192:inst|100'
            Info: 8: + IC(0.616 ns) + CELL(0.787 ns) = 10.679 ns; Loc. = LCFF_X64_Y1_N21; Fanout = 4; REG Node = '74192:inst|23'
            Info: 9: + IC(0.723 ns) + CELL(0.271 ns) = 11.673 ns; Loc. = LCCOMB_X62_Y1_N22; Fanout = 5; COMB Node = '74192:inst|77'
            Info: 10: + IC(0.253 ns) + CELL(0.787 ns) = 12.713 ns; Loc. = LCFF_X62_Y1_N11; Fanout = 6; REG Node = '74192:inst2|26'
            Info: 11: + IC(0.326 ns) + CELL(0.150 ns) = 13.189 ns; Loc. = LCCOMB_X62_Y1_N0; Fanout = 1; COMB Node = '74192:inst2|73'
            Info: 12: + IC(0.411 ns) + CELL(0.787 ns) = 14.387 ns; Loc. = LCFF_X62_Y2_N17; Fanout = 5; REG Node = '74192:inst2|25'
            Info: 13: + IC(0.533 ns) + CELL(0.438 ns) = 15.358 ns; Loc. = LCCOMB_X62_Y1_N20; Fanout = 1; COMB Node = '74192:inst2|51'
            Info: 14: + IC(0.623 ns) + CELL(0.787 ns) = 16.768 ns; Loc. = LCFF_X60_Y1_N3; Fanout = 3; REG Node = '74192:inst2|24'
            Info: 15: + IC(0.707 ns) + CELL(0.150 ns) = 17.625 ns; Loc. = LCCOMB_X62_Y1_N16; Fanout = 1; COMB Node = '74192:inst2|100~0'
            Info: 16: + IC(0.247 ns) + CELL(0.275 ns) = 18.147 ns; Loc. = LCCOMB_X62_Y1_N24; Fanout = 1; COMB Node = '74192:inst2|100'
            Info: 17: + IC(0.409 ns) + CELL(0.537 ns) = 19.093 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
            Info: Total cell delay = 9.424 ns ( 49.36 % )
            Info: Total interconnect delay = 9.669 ns ( 50.64 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Warning: Circuit may not operate. Detected 7 non-operational path(s) clocked by clock "clock" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "74192:inst2|23" and destination pin or register "74192:inst2|23" for clock "clock" (Hold time is 13.648 ns)
    Info: + Largest clock skew is 14.039 ns
        Info: + Longest clock path from clock "clock" to destination register is 19.093 ns
            Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
            Info: 2: + IC(2.341 ns) + CELL(0.787 ns) = 3.990 ns; Loc. = LCFF_X63_Y2_N17; Fanout = 6; REG Node = '74192:inst|26'
            Info: 3: + IC(0.728 ns) + CELL(0.419 ns) = 5.137 ns; Loc. = LCCOMB_X62_Y1_N26; Fanout = 1; COMB Node = '74192:inst|73'
            Info: 4: + IC(0.408 ns) + CELL(0.787 ns) = 6.332 ns; Loc. = LCFF_X63_Y1_N15; Fanout = 3; REG Node = '74192:inst|25'
            Info: 5: + IC(0.457 ns) + CELL(0.420 ns) = 7.209 ns; Loc. = LCCOMB_X62_Y1_N14; Fanout = 2; COMB Node = '74192:inst|51'
            Info: 6: + IC(0.381 ns) + CELL(0.787 ns) = 8.377 ns; Loc. = LCFF_X61_Y1_N17; Fanout = 4; REG Node = '74192:inst|24'
            Info: 7: + IC(0.506 ns) + CELL(0.393 ns) = 9.276 ns; Loc. = LCCOMB_X62_Y1_N18; Fanout = 1; COMB Node = '74192:inst|100'
            Info: 8: + IC(0.616 ns) + CELL(0.787 ns) = 10.679 ns; Loc. = LCFF_X64_Y1_N21; Fanout = 4; REG Node = '74192:inst|23'
            Info: 9: + IC(0.723 ns) + CELL(0.271 ns) = 11.673 ns; Loc. = LCCOMB_X62_Y1_N22; Fanout = 5; COMB Node = '74192:inst|77'
            Info: 10: + IC(0.253 ns) + CELL(0.787 ns) = 12.713 ns; Loc. = LCFF_X62_Y1_N11; Fanout = 6; REG Node = '74192:inst2|26'
            Info: 11: + IC(0.326 ns) + CELL(0.150 ns) = 13.189 ns; Loc. = LCCOMB_X62_Y1_N0; Fanout = 1; COMB Node = '74192:inst2|73'
            Info: 12: + IC(0.411 ns) + CELL(0.787 ns) = 14.387 ns; Loc. = LCFF_X62_Y2_N17; Fanout = 5; REG Node = '74192:inst2|25'
            Info: 13: + IC(0.533 ns) + CELL(0.438 ns) = 15.358 ns; Loc. = LCCOMB_X62_Y1_N20; Fanout = 1; COMB Node = '74192:inst2|51'
            Info: 14: + IC(0.623 ns) + CELL(0.787 ns) = 16.768 ns; Loc. = LCFF_X60_Y1_N3; Fanout = 3; REG Node = '74192:inst2|24'
            Info: 15: + IC(0.707 ns) + CELL(0.150 ns) = 17.625 ns; Loc. = LCCOMB_X62_Y1_N16; Fanout = 1; COMB Node = '74192:inst2|100~0'
            Info: 16: + IC(0.247 ns) + CELL(0.275 ns) = 18.147 ns; Loc. = LCCOMB_X62_Y1_N24; Fanout = 1; COMB Node = '74192:inst2|100'
            Info: 17: + IC(0.409 ns) + CELL(0.537 ns) = 19.093 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
            Info: Total cell delay = 9.424 ns ( 49.36 % )
            Info: Total interconnect delay = 9.669 ns ( 50.64 % )
        Info: - Shortest clock path from clock "clock" to source register is 5.054 ns
            Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
            Info: 2: + IC(2.404 ns) + CELL(0.149 ns) = 3.415 ns; Loc. = LCCOMB_X62_Y1_N22; Fanout = 5; COMB Node = '74192:inst|77'
            Info: 3: + IC(0.273 ns) + CELL(0.420 ns) = 4.108 ns; Loc. = LCCOMB_X62_Y1_N24; Fanout = 1; COMB Node = '74192:inst2|100'
            Info: 4: + IC(0.409 ns) + CELL(0.537 ns) = 5.054 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
            Info: Total cell delay = 1.968 ns ( 38.94 % )
            Info: Total interconnect delay = 3.086 ns ( 61.06 % )
    Info: - Micro clock to output delay of source is 0.250 ns
    Info: - Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X62_Y1_N12; Fanout = 1; COMB Node = '74192:inst2|23~1'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 0.266 ns
Info: tco from clock "clock" to destination pin "O0" through register "74192:inst2|23" is 22.774 ns
    Info: + Longest clock path from clock "clock" to source register is 19.093 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(2.341 ns) + CELL(0.787 ns) = 3.990 ns; Loc. = LCFF_X63_Y2_N17; Fanout = 6; REG Node = '74192:inst|26'
        Info: 3: + IC(0.728 ns) + CELL(0.419 ns) = 5.137 ns; Loc. = LCCOMB_X62_Y1_N26; Fanout = 1; COMB Node = '74192:inst|73'
        Info: 4: + IC(0.408 ns) + CELL(0.787 ns) = 6.332 ns; Loc. = LCFF_X63_Y1_N15; Fanout = 3; REG Node = '74192:inst|25'
        Info: 5: + IC(0.457 ns) + CELL(0.420 ns) = 7.209 ns; Loc. = LCCOMB_X62_Y1_N14; Fanout = 2; COMB Node = '74192:inst|51'
        Info: 6: + IC(0.381 ns) + CELL(0.787 ns) = 8.377 ns; Loc. = LCFF_X61_Y1_N17; Fanout = 4; REG Node = '74192:inst|24'
        Info: 7: + IC(0.506 ns) + CELL(0.393 ns) = 9.276 ns; Loc. = LCCOMB_X62_Y1_N18; Fanout = 1; COMB Node = '74192:inst|100'
        Info: 8: + IC(0.616 ns) + CELL(0.787 ns) = 10.679 ns; Loc. = LCFF_X64_Y1_N21; Fanout = 4; REG Node = '74192:inst|23'
        Info: 9: + IC(0.723 ns) + CELL(0.271 ns) = 11.673 ns; Loc. = LCCOMB_X62_Y1_N22; Fanout = 5; COMB Node = '74192:inst|77'
        Info: 10: + IC(0.253 ns) + CELL(0.787 ns) = 12.713 ns; Loc. = LCFF_X62_Y1_N11; Fanout = 6; REG Node = '74192:inst2|26'
        Info: 11: + IC(0.326 ns) + CELL(0.150 ns) = 13.189 ns; Loc. = LCCOMB_X62_Y1_N0; Fanout = 1; COMB Node = '74192:inst2|73'
        Info: 12: + IC(0.411 ns) + CELL(0.787 ns) = 14.387 ns; Loc. = LCFF_X62_Y2_N17; Fanout = 5; REG Node = '74192:inst2|25'
        Info: 13: + IC(0.533 ns) + CELL(0.438 ns) = 15.358 ns; Loc. = LCCOMB_X62_Y1_N20; Fanout = 1; COMB Node = '74192:inst2|51'
        Info: 14: + IC(0.623 ns) + CELL(0.787 ns) = 16.768 ns; Loc. = LCFF_X60_Y1_N3; Fanout = 3; REG Node = '74192:inst2|24'
        Info: 15: + IC(0.707 ns) + CELL(0.150 ns) = 17.625 ns; Loc. = LCCOMB_X62_Y1_N16; Fanout = 1; COMB Node = '74192:inst2|100~0'
        Info: 16: + IC(0.247 ns) + CELL(0.275 ns) = 18.147 ns; Loc. = LCCOMB_X62_Y1_N24; Fanout = 1; COMB Node = '74192:inst2|100'
        Info: 17: + IC(0.409 ns) + CELL(0.537 ns) = 19.093 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: Total cell delay = 9.424 ns ( 49.36 % )
        Info: Total interconnect delay = 9.669 ns ( 50.64 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.431 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y1_N13; Fanout = 4; REG Node = '74192:inst2|23'
        Info: 2: + IC(0.633 ns) + CELL(2.798 ns) = 3.431 ns; Loc. = PIN_AC21; Fanout = 0; PIN Node = 'O0'
        Info: Total cell delay = 2.798 ns ( 81.55 % )
        Info: Total interconnect delay = 0.633 ns ( 18.45 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Wed Oct 19 10:51:38 2011
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01


