Classic Timing Analyzer report for d
Wed Dec 07 11:04:53 2011
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clock'
  6. tco
  7. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                      ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                                    ; From          ; To            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+
; Worst-case tco               ; N/A   ; None          ; 9.542 ns                                       ; DFF2:inst25|3 ; O3            ; clock      ; --       ; 0            ;
; Clock Setup: 'clock'         ; N/A   ; None          ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst|3   ; DFF2:inst25|3 ; clock      ; clock    ; 0            ;
; Total number of failed paths ;       ;               ;                                                ;               ;               ;            ;          ; 0            ;
+------------------------------+-------+---------------+------------------------------------------------+---------------+---------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                           ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                              ; Setting            ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                         ; EP2C35F672C6       ;      ;    ;             ;
; Timing Models                                                       ; Final              ;      ;    ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;    ;             ;
; Enable Clock Latency                                                ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;    ;             ;
; Minimum Core Junction Temperature                                   ; 0                  ;      ;    ;             ;
; Maximum Core Junction Temperature                                   ; 85                 ;      ;    ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;    ;             ;
; Number of paths to report                                           ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;    ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;    ;             ;
; Output I/O Timing Endpoint                                          ; Near End           ;      ;    ;             ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clock'                                                                                                                                                                               ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From          ; To            ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst|3   ; DFF2:inst25|3 ; clock      ; clock    ; None                        ; None                      ; 1.020 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst25|3 ; DFF2:inst|3   ; clock      ; clock    ; None                        ; None                      ; 0.920 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst25|3 ; DFF2:inst23|3 ; clock      ; clock    ; None                        ; None                      ; 0.917 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst25|3 ; DFF2:inst22|3 ; clock      ; clock    ; None                        ; None                      ; 0.913 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst23|3 ; DFF2:inst25|3 ; clock      ; clock    ; None                        ; None                      ; 0.891 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst23|3 ; DFF2:inst22|3 ; clock      ; clock    ; None                        ; None                      ; 0.890 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst23|3 ; DFF2:inst|3   ; clock      ; clock    ; None                        ; None                      ; 0.883 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst|3   ; DFF2:inst23|3 ; clock      ; clock    ; None                        ; None                      ; 0.882 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst|3   ; DFF2:inst22|3 ; clock      ; clock    ; None                        ; None                      ; 0.615 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst22|3 ; DFF2:inst|3   ; clock      ; clock    ; None                        ; None                      ; 0.607 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst22|3 ; DFF2:inst23|3 ; clock      ; clock    ; None                        ; None                      ; 0.605 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst22|3 ; DFF2:inst25|3 ; clock      ; clock    ; None                        ; None                      ; 0.602 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst25|3 ; DFF2:inst25|3 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst23|3 ; DFF2:inst23|3 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst|3   ; DFF2:inst|3   ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
; N/A   ; Restricted to 450.05 MHz ( period = 2.222 ns ) ; DFF2:inst22|3 ; DFF2:inst22|3 ; clock      ; clock    ; None                        ; None                      ; 0.407 ns                ;
+-------+------------------------------------------------+---------------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+---------------+----+------------+
; Slack ; Required tco ; Actual tco ; From          ; To ; From Clock ;
+-------+--------------+------------+---------------+----+------------+
; N/A   ; None         ; 9.542 ns   ; DFF2:inst25|3 ; O3 ; clock      ;
; N/A   ; None         ; 9.513 ns   ; DFF2:inst22|3 ; O1 ; clock      ;
; N/A   ; None         ; 9.406 ns   ; DFF2:inst25|3 ; H0 ; clock      ;
; N/A   ; None         ; 9.387 ns   ; DFF2:inst25|3 ; H2 ; clock      ;
; N/A   ; None         ; 9.383 ns   ; DFF2:inst|3   ; H0 ; clock      ;
; N/A   ; None         ; 9.375 ns   ; DFF2:inst25|3 ; H4 ; clock      ;
; N/A   ; None         ; 9.374 ns   ; DFF2:inst25|3 ; H3 ; clock      ;
; N/A   ; None         ; 9.368 ns   ; DFF2:inst25|3 ; H1 ; clock      ;
; N/A   ; None         ; 9.353 ns   ; DFF2:inst|3   ; H2 ; clock      ;
; N/A   ; None         ; 9.345 ns   ; DFF2:inst|3   ; H1 ; clock      ;
; N/A   ; None         ; 9.331 ns   ; DFF2:inst|3   ; H3 ; clock      ;
; N/A   ; None         ; 9.323 ns   ; DFF2:inst|3   ; H4 ; clock      ;
; N/A   ; None         ; 9.284 ns   ; DFF2:inst23|3 ; O2 ; clock      ;
; N/A   ; None         ; 9.245 ns   ; DFF2:inst23|3 ; H0 ; clock      ;
; N/A   ; None         ; 9.208 ns   ; DFF2:inst23|3 ; H2 ; clock      ;
; N/A   ; None         ; 9.203 ns   ; DFF2:inst23|3 ; H1 ; clock      ;
; N/A   ; None         ; 9.202 ns   ; DFF2:inst23|3 ; H4 ; clock      ;
; N/A   ; None         ; 9.201 ns   ; DFF2:inst23|3 ; H3 ; clock      ;
; N/A   ; None         ; 9.139 ns   ; DFF2:inst25|3 ; H5 ; clock      ;
; N/A   ; None         ; 9.134 ns   ; DFF2:inst25|3 ; H6 ; clock      ;
; N/A   ; None         ; 9.113 ns   ; DFF2:inst|3   ; H5 ; clock      ;
; N/A   ; None         ; 9.110 ns   ; DFF2:inst|3   ; H6 ; clock      ;
; N/A   ; None         ; 9.097 ns   ; DFF2:inst22|3 ; H0 ; clock      ;
; N/A   ; None         ; 9.075 ns   ; DFF2:inst22|3 ; H2 ; clock      ;
; N/A   ; None         ; 9.062 ns   ; DFF2:inst22|3 ; H4 ; clock      ;
; N/A   ; None         ; 9.062 ns   ; DFF2:inst22|3 ; H3 ; clock      ;
; N/A   ; None         ; 9.059 ns   ; DFF2:inst22|3 ; H1 ; clock      ;
; N/A   ; None         ; 9.036 ns   ; DFF2:inst|3   ; O0 ; clock      ;
; N/A   ; None         ; 8.974 ns   ; DFF2:inst23|3 ; H5 ; clock      ;
; N/A   ; None         ; 8.973 ns   ; DFF2:inst23|3 ; H6 ; clock      ;
; N/A   ; None         ; 8.825 ns   ; DFF2:inst22|3 ; H6 ; clock      ;
; N/A   ; None         ; 8.825 ns   ; DFF2:inst22|3 ; H5 ; clock      ;
+-------+--------------+------------+---------------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
    Info: Processing started: Wed Dec 07 11:04:52 2011
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off d -c d --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 450.05 MHz between source register "DFF2:inst|3" and destination register "DFF2:inst25|3"
    Info: fmax restricted to clock pin edge rate 2.222 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.020 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y1_N3; Fanout = 12; REG Node = 'DFF2:inst|3'
            Info: 2: + IC(0.361 ns) + CELL(0.659 ns) = 1.020 ns; Loc. = LCFF_X37_Y1_N25; Fanout = 12; REG Node = 'DFF2:inst25|3'
            Info: Total cell delay = 0.659 ns ( 64.61 % )
            Info: Total interconnect delay = 0.361 ns ( 35.39 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 4.239 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(2.840 ns) + CELL(0.537 ns) = 4.239 ns; Loc. = LCFF_X37_Y1_N25; Fanout = 12; REG Node = 'DFF2:inst25|3'
                Info: Total cell delay = 1.399 ns ( 33.00 % )
                Info: Total interconnect delay = 2.840 ns ( 67.00 % )
            Info: - Longest clock path from clock "clock" to source register is 4.239 ns
                Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
                Info: 2: + IC(2.840 ns) + CELL(0.537 ns) = 4.239 ns; Loc. = LCFF_X37_Y1_N3; Fanout = 12; REG Node = 'DFF2:inst|3'
                Info: Total cell delay = 1.399 ns ( 33.00 % )
                Info: Total interconnect delay = 2.840 ns ( 67.00 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clock" to destination pin "O3" through register "DFF2:inst25|3" is 9.542 ns
    Info: + Longest clock path from clock "clock" to source register is 4.239 ns
        Info: 1: + IC(0.000 ns) + CELL(0.862 ns) = 0.862 ns; Loc. = PIN_G26; Fanout = 4; CLK Node = 'clock'
        Info: 2: + IC(2.840 ns) + CELL(0.537 ns) = 4.239 ns; Loc. = LCFF_X37_Y1_N25; Fanout = 12; REG Node = 'DFF2:inst25|3'
        Info: Total cell delay = 1.399 ns ( 33.00 % )
        Info: Total interconnect delay = 2.840 ns ( 67.00 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.053 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X37_Y1_N25; Fanout = 12; REG Node = 'DFF2:inst25|3'
        Info: 2: + IC(2.235 ns) + CELL(2.818 ns) = 5.053 ns; Loc. = PIN_AE23; Fanout = 0; PIN Node = 'O3'
        Info: Total cell delay = 2.818 ns ( 55.77 % )
        Info: Total interconnect delay = 2.235 ns ( 44.23 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 134 megabytes
    Info: Processing ended: Wed Dec 07 11:04:53 2011
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:01


